high precision wraparound - high temperature (230 c) thin film chip resistors pht vishay sfernice www.vishay.com for technical questions, contact: sfer@vishay.com document number: 53050 1 revision: 10-aug-10 introduction for applications such as down hole applications, the need for parts able to withstand very severe conditions (temperature as high as 215 c powered or up to 230 c un-powered) has leaded vishay sfernice to push out the limit of the thin film technology. designers might read the application note: power dissipation considerations in high precision vishay sfernice thin film chip resistors and arrays (p, pra etc?) (high temperature application) www.vishay.com/doc?53047 in conjunction with this datasheet to help them to properly design their pcbs and get the best performances of the pht. vishay sfernice r&d engineers will be willing to support any customer design considerations. features ? operating temperature range: - 55 c; + 215 c ? storage temperature: - 55 c; + 230 c ? gold terminations (< 1 m thick) ? 4 sizes available (0603, 0805, 1206, 2010) - other sizes upon request ? temperature coefficient down to 25 ppm (- 55 c; + 215 c) ? tolerance down to 0.05 % ? load life stability: 0.5 % max after 1000 h at 215 c (ambient) at pn ? smd wraparound ? compliant to rohs directive 2002/95/ec dimensions in millimeters (inches) ** please see document ?vishay material category policy?: www.vishay.com/doc?99902 case size ab c d/e max. tol. + 0.152 (+ 0.006) min. tol. - 0.152 (- 0.006) max. tol. + 0.127 (+ 0.005) min. tol. - 0.127 (- 0.005) nominal nominal nominal tolerance 0603 1.52 (0.060) 0.85 (0.033) 0.5 (0.02) 0.127 (0.005) 0.38 (0.015) 0.13 (0.005) 0805 1.91 (0.075) 1.27 (0.050) 1206 3.06 (0.120) 1.60 (0.063) 0.40 (0.016) 2010 5.08 (0.200) 2.54 (0.100) 0.48 (0.019) a d d c e e b
pht high precision wraparound - high temperature (230 c) thin film chip resistors vishay sfernice document number: 53050 for technical questions, contact: sfer@vishay.com www.vishay.com revision: 10-aug-10 2 suggested land pattern (to ipc-7351a) notes (1) please refer to table 3 for tcr versus ohmic values (2) see table 2 (3) see table 1 caution : performances obtained with following mounting conditions: pcb: polyimide solder paste: pbsnag (93.5/5/1.5) chip size dimensions (in millimeter) z max. g min. x max. 0603 2.37 0.35 0.98 0805 2.76 0.74 1.40 1206 3.91 1.85 1.73 2010 5.93 3.71 2.67 standard electrical specifications test specifications conditions series 0603, 0805, 1206, 2010 ohmic range (1) 10r to 7m6 (depending on series) temperature coefficient (2) 25 ppm/c, 50 ppm/c, 100 ppm/c - 55 c; + 215 c tolerance 0.05 %, 0.1 %, 0.5 %, 1 % power rating (pn) (3) 12.5 mw to 100 mw 215 c operating temperature range - 55 c; + 215 c limiting voltage (3) 75 v to 300 v load life stability 0.50 % 1000 h/215 c (ambient) at pn storage temperature range - 55 c; + 230 c shelf life stability 0.7 % typ. (1 % max.) 8000 h/230 c g min. z max. x max.
pht vishay sfernice high precision wraparound - high temperature (230 c) thin film chip resistors www.vishay.com for technical questions, contact: sfer@vishay.com document number: 53050 3 revision: 10-aug-10 note (1) for power handling improvement, please refer to application note 53047: power dissipation consider ations in high precision vish ay sfernice thin film chip resistors and arrays (high temperature applications) www.vishay.com/doc?/53047 and consult vishay sfernice note (2) best tolerance possible: 0.5 %: 10 to < 20 0.1 %: 20 to < 39 0.05 %: 39 to max. value pht stability curve note ? stability will be dependent on resistivity of resistor. above curves are worst case. ta b l e 1 size power rating (1) limiting voltage 0603 12.5 mw 75 v 0805 20 mw 150 v 1206 33 mw 200 v 2010 100 mw 300 v table 2 - temperature coefficient y 10 ppm/c - 55 c; + 155 c 25 ppm/c - 55 c; + 215 c e 25 ppm/c - 55 c; + 155 c 50 ppm/c - 55 c; + 215 c h 50 ppm/c - 55 c; + 155 c 100 ppm/c - 55 c; + 215 c ta b l e 3 series ohmic range (2) ct: y ct: e/h min. max. min. max. 0603 39 320k 10 320k 0805 39 511k 10 725k 1206 39 1m8 10 2m7 2010 39 5m 10 7m6 0.0 8 000 drift in % time in h hi g h temperature drift vs. time 0 1000 2000 3000 4000 5000 6000 7000 0.1 0.2 0.3 0.4 0.5 0.6 0.7 w ith pd (t j = 230 c) t = 1 8 5 c t = 200 c t = 215 c t = 230 c
pht high precision wraparound - high temperature (230 c) thin film chip resistors vishay sfernice document number: 53050 for technical questions, contact: sfer@vishay.com www.vishay.com revision: 10-aug-10 4 note ? for other terminations, please consult popular options it is recommended to consult vishay sfernice for availability first. option: enlarged terminations: for stringent and special power dissipation requirements, the therma l resistance between the resistive layer and the solder joi nt can be reduced using enlarged terminations chip resistors which ar e soldered on large and thick copper pads acting as heatsink (see application note: 53048 power dissipation in high precision vi shay sfernice chip resistors and arrays (p thin film, pra arrays, chp thick film) www.vishay.com/doc?53048 . option to order: 0063 (applies to size 1206/2010). dimensions (option 0063) in millimeters suggested land pattern (option 0063) mechanical specifications substrate alumina resistive element nichrome (nicr) passivation silicon nitride (si 3 n 4 ) protection epoxy + silicone terminations gold (< 1 m) over nickel barrier case size abed f max. tol. + 0.152 min. tol. - 0.152 max. tol. + 0.127 min. tol. - 0.127 max. tol. + 0.13 min. tol. - 0.13 max. tol. + 0.13 min. tol. - 0.13 nominal nominal nominal nominal nominal min. max. 1206 3.06 1.60 0.40 1.215 0.63 0.50 0.76 2010 5.08 2.54 0.48 2.25 chip size dimensions (in millimeter) z max. g min. x max. 1206 3.91 0.50 1.73 2010 5.93 2.67 a b d e f enlarged termination uncoated ceramic bottom view for mountin g g min. z max. x max.
pht vishay sfernice high precision wraparound - high temperature (230 c) thin film chip resistors www.vishay.com for technical questions, contact: sfer@vishay.com document number: 53050 5 revision: 10-aug-10 packaging esd packaging available: waffle-pack, and plastic tape and reel (low conductivity). paper tape available upon request (esd only). note (1) 12 mm on request packaging rules waffle pack can be filled up to maximum quantity indicated in the table here above, taking into account the minimum order quantity. when quantity ordered exce eds maximum quantity of a single waffle pack, the waffle packs are stacked up on the top of each other and closed by one single cover. to get ?not stacked up? waffle pack in case of ordered quantity > maximum number of pieces per package: please consult vishay sfer nice for specific ordering code tape and reel can be filled up to maximum quantity indicated in the table here above, taking into account the minimum order quantity. when quantity ordered is between the moq and the maximum reel capacity, only one reel is provided. when several reels are n eeded for ordered quantity within moq and maximum reel capacity: please consult vishay sfernice for specific ordering code note (2) for usage at temperatures up to 200 c maximum n (tin/silver terminati on are available upon request) size moq number of pieces per package tape width waffle pack 2 " 2 " tape and reel min. max. 0603 100 100 100 4000 8 mm 0805 1206 140 2010 60 2000 8 mm (1) global part number information global part numbering: pht1206y1001bgt063 global model size tcr value tolerance termination packaging option pht 0603 0805 1206 2010 y e h the first three digits are significant figures and the last digit specifies the number of zeros to follow, r designates decimal point 10r0 = 10 3901 = 3900 1004 = 1 m w = 0.05 % b = 0.1 % d = 0.5 % f = 1 % g = gold n = tin/silver (2) t = tape and reel blank = waffle pack leave blank if no option ht1206y10 p 01bgt 06 3
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